5. NPAP Techbriefs

The following technical briefs provide additional information regarding the configuration, benchmarking, and integration aspects of the NPAP IP core.

• Latency Measurement of 10G/25G/50G/100G TCP-Cores Using RTL Simulation: Details the methodology for measuring “door-to-door” latency of the NPAP TCP/IP stack.

• Put a TCP/UDP/IP Turbo Into Your FPGA-SmartNIC: Describes combining the Corundum NIC with NPAP to create a high-throughput SmartNIC solution.

• Smart Data Diodes: Covers the transition from classical data diodes to smart, FPGA-based solutions.

• High-Speed Data Acquisition System: Addresses the challenges of high-speed data acquisition and the role of TCP offload engines.

• Myth-Busting Latency Numbers for TCP Offload Engines: Critiques common latency measurement methods and proposes counting clock cycles in RTL simulation.

• Analyzing Network Impairment and Signal Integrity in High-Speed TCP/UDP/IP Ethernet Networks: Discusses diagnosing network impairment, iBERT signal integrity, and FPGA-based impairment generation.

• A TCP/IP Stack for High-Performance Chip-to-Chip: Highlights the advantages of NPAP for distributed systems and protocol tunneling for AXI interfaces.