To read the full content, please log in or register as an MLE Developer Zone Member.
3.1. NPAP Technical Features FeatureSpecificationSupported on-chip Interfaces128 bit wide AXI4-StreamCompatibility with 3rd party Ethernet PHY interfacesStandard IEEE Ethernet PHYs with RMII, GMII, XGMII, etc via PCS/PMA via ASIC/FPGA Ethernet SubsystemCompatibility with 3rd party Ethernet Media Access ControllersFraunhofer HHI 10G/25G Low-Latency MACAMD/Xilinx 10G/25G Ethernet Subsystem (PG210)AMD/Xilinx 100G Ethernet Subsystem (PG165, PG203, PG314)Altera 10G / 25G Ethernet FPGA IPMicrochip PolarFire FPGA 10G Ethernet (UG0727)Lattice 10G / 25G Ethernet IP (FPGA-IPUG-02245)Supported protocols (Hardware based)Ethernet, ARP, IPv4, ICMPv4 (response only), IGMPv4, UDP & TCP, DHCP (client only)Number of simultaneous connectionsOne per TCP Core instantiation – see “Architecture Choices” below, a TCP Core in NPAP relates to a TCP socket in LinuxMessage SizesSupport for Ethernet Jumbo Frames of arbitrary lengthInterface to applicationDatapath via AXI4-Stream 128-bitand separate custom TCP command interfaceSupported FPGAs Complete stack uses generic VHDL code (IEEE-1076 2002 or 2008, depending on NPAP version)AMD/Xilinx Virtex 4 to Virtex UltraScale+AMD/Xilinx Kintex to Kintex UltraScale+AMD/Xilinx Artix UltraScale+AMD/Xilinx Zynq-7000AMD/Xilinx Zynq UltraScale+ MPSoCAMD/Xilinx Zynq UltraScale+ RFSoCAMD/Xilinx Versal ACAP SeriesAltera Cyclone IV seriesAltera Cyclone 10 GX seriesAltera Stratix VAltera Stratix 10 GX seriesAltera Agilex 5 D, E SeriesAltera Agilex 7 F, I, M SeriesLattice Avant-G, Avant-XMicrochip Polarfire and PolarFire SoCPerformance70 Gbps line rate, or more, for single TCP/IPv4 session (depending on clock rate, see below)Typ. 600 ns transport delay (depending on