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1. NPAP Features With a focus on reliability and low, deterministic latency, HHI designed this for embeddable FPGA and ASIC systems with the following features: Interface to 1 / 2.5 / 5 / 10 / 25 / 40 / 50 / 100 / 200 / 400 Gigabit Ethernet (depending on the FPGA device and speedgrade.) Full-duplex with 128 bit wide bidirectional datapath Full line rate of 70 Gbps, or more, per instance in FPGA Full line rate of over 100 Gbps per instance in ASIC Low one-way latency NPAP-to-NPAP (600 nanoseconds for 100 Bytes) Network diagnostics functions (optional) TCP session priority management (optional) Transport Layer Security (TLS) (optional) Time-Sensitive Networking (TSN) (optional) Network Impairment Generators (optional) Designed for maximum flexibility, NPAP implements in programmable logic the relevant network communication protocols: IPv4 The core of the most standards-based networking protocols TCP Reliable connectivity for direct secured connectivity UDP Widespread protocol to enable simple direct or multicast communication RRRRP Reliable, Rapid Request-Response Protocol based on Stanford HOMA ICMPv4 Diagnostic protocol to validate connections IGMPv4 Enables joining of multicast groups (optional) Due to the modularity NPAP can easily be enhanced by application specific protocols. The 128 bit wide datapath in combination with a pipelined architecture allows to scale throughput to line-rates of 50 GbE, and
