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3.4. NPAP Control-Flow View and Hardware Abstraction Layer For administration and control at run-time, NPAP implements so-called Runtime Parameterization and administration via an AXI-Lite register space. Access to this interface is exported through the so-called NPAP Hardware Abstraction Layer (HAL). Along with a Python library, NPAP HAL provides a high-level API for Linux software, utilizing swappable backends to communicate with the hardware across diverse environments, from SOC processing systems to remote workstations. Here a list of connectivity choices for NPAP HAL: Via USB-UART or USB-JTAG or USB-IIC Via the FPGA-integrated Processing System which can be ARM, RISC-V, MicroBlaze, NIOS, etc Via PCIe connection with the host CPU Via out-of-band Ethernet and UDP (on the roadmap) Via in-band Ethernet and UDP (on the roadmap) Besides NPAP HAL, MLE further provides a python based command-line tool, called npap-admin, that abstracts complex runtime parameterization into simple configuration file editing. Customers have been using npap-admin during evaluation and development, for Continuous Integration or in-the-field when NPAP-based products have been deployed. Good design examples for Runtime parameterization and administration of NPAP are the so-called NPAP Evaluation Reference Designs (ERD) running on many off-the-shelf FPGA platforms. Please read below for more information. 3.4.1. NPAP Admin via USB-UART or USB-JTAG This mode of administration is very useful when using