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3.2. NPAP Implementation Details NPAP implements a full accelerator, hence all network protocol processing is running as digital logic. Because NPAP does not rely on “soft” CPUs nor on external CPUs, NPAP shows very low and deterministic latency. Tradeoff cost vs performance over chip resources. Dataflow is full duplex 128 bits wide using AXI4 Stream. This enables high data throughput without “FPGA bloat” nor timing issues. Control-flow uses AXI4 Lite register interfaces, along with a hardware abstraction layer (HAL), Linux device drivers and Python scripts for NPAP administration. NPAP is intensively tested for performance and interoperability against many other TCP/UDP/IPv4 network stacks. NPAP brings its own 10G / 25G Low-Latency Ethernet MAC,but can interface with many Ethernet subsystems from the FPGA vendors. NPAP implements a complete TCP/UDP/IPv4 stack including functions like ARP, ICMPv4, IGMPv4, DHCP. NPAP is delivered with “Support IP blocks” including reference designs, design examples for setting MAC addresses and/or IPv4 addresses and/or TCP port numbers either from Programmable Logic / ASIC or via software running on a (Linux) host, either ARM or x86 based. For each TCP connection that remains open at the same time, there shall be a dedicated instance of a TCP Core. An AXI4-Lite interface may be used to prioritize TCP sessions during runtime. One and