AMD/Xilinx Zynq UltraScale+ MPSoC PS Mali GPU to PL

September 27, 2023Application Notes, I/O Connectivitydisplay, DRI, DRM, EGL, eglfs, KMS, Live Video, LVDS, Mali, MIPI DSI/CSI, OpenGL, OpenGL ES, PetaLinux, PS-PL, Qt, SDI, Vivado, ZYNQ UltraScale+ MPSoC

AMD/Xilinx Zynq UltraScale+ MPSoC PS Mali GPU to PL

Objective

Sometimes it is necessary to direct the output of the AMD/Xilinx Zynq UltraScale+ MPSoC integrated Mali GPU to the FPGA PL. One example of such a use case is running Linux, rendering hardware accelerated OpenGL applications, and displaying the results on a PL attached LVDS, MIPI DSI/CSI, HDMI, or SDI display. The readily available output options for the Mali GPU are limited to PS attached DisplayPort via GTR transceivers. The following describes how Mali GPU video output can be directed to the FPGA PL nonetheless, to enable a broader range of interface options.

Table of Contents

AMD/Xilinx Zynq UltraScale+ MPSoC PS Mali GPU to PL

USB 2.0 Host Dev Guide

December 16, 2014Application Notes, I/O ConnectivityUSB Host Controller IP

XPS USB Host Controller Developer’s Guide

TB20141216

This MLE Technical Brief is intended for embedded systems and FPGA designers who seek to integrate the XPS_USB_HOST Controller IP Core. Originally developed and shipped by Xilinx, Inc. MLE has been marketing and supporting this IP core for Xilinx customers, since October 2011. This Technical Brief gives you an introduction into the functionality of USB 2.0 in general, describes the usage in a FPGA design and provides references to further documentation.

Foundation of this Technical Brief is the XPS_USB_Host Controller Linux Reference Design from MLE. Using this reference design the various modes of USB can be evaluated based on some basic and easy to reproduce test-cases. This highlights how the
XPS_USB_HOST Controller IP Core operates in conjunction with Linux running on an embedded CPU (Xilinx MicroBlaze or PowerPC) inside a Xilinx FPGA device.

Nios-II Multiboot

October 12, 2011Application Notes, I/O ConnectivitySoM Adjustment

Configurable Systems in Altera Stratix-IV FPGAs

TB20111012

This Technical Brief describes a Configurable System based on Altera’s Nios-II processor running MLE’s “Soft” Hardware Platform, integrated into Terasic’s DE4 Development Kit. The system implements a complete Single-Board Computer (SBC) which supports a multistage boot process to provide software-based flexibility for different Linux software stacks.

FPGA + integrated DAC

April 26, 2011Application Notes, I/O ConnectivityDAC, Mixed Signal

Integrated DAC for Altera Cyclone-IV Devices

TB20110426

This Technical Brief explains the use of Delta Sigma Modulation to implement resource-efficient Digital-to-Analog Converter (DAC) in Altera FPGA devices. Starting with an introduction into the technology of Delta Sigma Modulation, we will cover the relevant technical aspects for implementing and applying this as a flexible and cost-efficient means for DAC. We will provide the results of diligent testing using Altera Cyclone-IV FPGA devices which led to our technical specifications (Signal-to-Noise Ratios, Total Harmonic Distortion, Spurios-Free Dynamic Range values) including results for higher order modulators.

FPGA + integrated ADC

April 19, 2011Application Notes, I/O ConnectivityADC, Mixed Signal

Integrated ADC for Altera Cyclone-IV Devices

TB20110419

This Technical Brief describes how to use Delta Sigma Modulation to implement resource-efficient Analog-to-Digital Converters (ADC) in Altera FPGA devices. Starting with an introduction into the technology of Delta Sigma Modulation, we will cover the relevant technical aspects for implementing and applying this as a flexible and cost-efficient means for ADC. We will provide the results of diligent testing using Altera Cyclone-IV FPGA devices which led to our technical specifications (Signal-to-Noise Ratios, Linearity, Spurious-Free Dynamic Range values).

Linux SysFS

January 27, 2011Application Notes, I/O Connectivity

Hardware Parameter Access from Application Software

TB20110127

We present a technique for accessing hardware device paramenters and control values based on the Open Source GNU/Linux standardized concept of the sysfs virtual filesystem. Exemplary code for a motor control device demonstrates how to easily access a hardware device’s registers from application software and/or user scripts to facilitate hardware integration or system debugging.

USB Hot-Plug for UMTS

May 7, 2010Application Notes, I/O Connectivity

Using USB Hot-Plug for UMTS Short Message Service

TB20100507

This Technical Brief describes how the USB hot-plug capabilities of the MLE “Soft” Hardware Platform can be used to quickly connect USB-based consumer electronic devices. In an exemplary setup, we demonstrate how to connect an off-the-shelf Universal Mobile Telecommunications System (UMTS) modem device to extend the MLE “Soft” Hardware Platform with UMTS/GSM connectivity. We will present an Open Source based solution, which goes beyond a simple Short Message Service (SMS) and which can, for example, be used for remote monitoring and administration of sensor networks in the field.

Network Connectivity

February 18, 2010Application Notes, I/O Connectivity

Network Connectivity of MLE 1000 Series

TB20100218

This Technical Brief describes the capabilities of the Missing Link Electronics 1000 Series Rapid Prototyping System to connect to a corporate network or to the Internet. The integrated network connectivity enables sharing the prototyping system among multiple users over separate locations or to utilize other compute and storage resources within a corporate network.

Bluetooth Testing

February 2, 2010Application Notes, I/O Connectivity

Automated Testing of Bluetooth Connectivity

TB20100202

Testing Bluetooth is hard. Harder when development cycles of the connection partners significantly differ, such as those of mobile phones and their counterparts in the automotive or industrial field. It gets even harder when the systems under test have to fulfill the high expectations consumers have.

This technical brief describes a setup for automated testing of Bluetooth connectivity. At first a short overview over Bluetooth is given. Afterwards different setups utilizing the MLE 1000 Series Rapid Prototyping System and the power of the MLE Linux operating system are described. Furthermore a framework for automation of Bluetooth testing and chip level analysis of Bluetooth communication is demonstrated. Then we have a detailed look on a Hands Free Profile communication. Finally more advanced testing methods, which make use of the FPGA in the MLE 1000 Series Rapid Prototyping System are mentioned.

TFT Image Analysis

January 29, 2010Application Notes, I/O Connectivity

Deep Image Analysis for Multimedia Systems

TB20100129

Debugging a video image system, especially if multiple displays are involved, can be a very hard task. Pixel-accurate and color-correct snapshots, triggered by external events and precisely timestamped can greatly aid the process. If additional real-time preprocessing of the video image stream can be accomplished, certain testing scenarios can profit even further. Utilizing the “Soft” Hardware of the MLE 1000 Series Rapid Prototyping System, a framework for simultaneous Deep Image Analysis of multiple displays is demonstrated.