AMD/Xilinx ZCU106 Archives - MLE Developer Zone

Mini, Midi, Big or Supersize – Motherboard Demo Solution for Proof of Concept (POC)

September 7, 2023FPGA DevTips, Lab SetupsAMD/Xilinx ZCU106, Commercial Off The Shelf (COTS), Hardware, Proof of Concept (POC)

Mini, Midi, Big or Supersize – Motherboard Demo Solution for Proof of Concept (POC) Our Mission: If It Is Packets, We Make It Go Faster! And with packets we mean: Networking using TCP/UDP/IP over 10G/25G/50G/100G Ethernet PCI Express (PCIe), CXL, OpenCAPI Data storage using SATA, SAS, USB, NVMe Video image processing using HDMI, DisplayPort, SDI, FPD-III. Working on a proof of concept (POC) can be challenging, no time, no custom tailored hardware but you need to deliver an appealing demo. The solution seems simple: commercial off the shelf hardware (COTS). However sometimes the outcome is on the other side of the spectrum you are planning to go. As an example: How do you mount a Xilinx ZCU106, which is nearly a double height and full length PCIe card on a Motherboard? Easy, just buy one of the biggest PC enclosures you find commercially available: A custom made front panel for the ZCU106 outputs completes the image – and voilà there is your nice POC demo you don’t have to be afraid to put in front of your customer. *Hint: Maybe bring a sketch of the final size hardware to show the difference. In this case it will be smaller than the ZCU106 itself. Contact Us Reference [1] https://www.thermaltake.com/level-20-xt.html 🌐 www.missinglinkelectronics.com MLE (Missing

Molex Mini-Fit Jr – Know your Power, and Don’t Get Confused – “PCIe” and “Xilinx Not PCIe” Power Connector

November 23, 2022FPGA DevTips, Lab SetupsAMD/Xilinx ZCU102, AMD/Xilinx ZCU106, Kintex, MolexMiniFit, Ultrascale, Virtex, Xilinx, Zynq

Molex Mini-Fit Jr – Know your Power, and Don’t Get Confused – “PCIe” and “Xilinx Not PCIe” Power Connector Table of ContentsMolex Mini-Fit Jr – Know your Power, and Don’t Get Confused – “PCIe” and “Xilinx Not PCIe” Power ConnectorPCI Express Cards Consumption LimitUsing Additional Connectors for Higher PCIe Card Consumption Our Mission: If It Is Packets, We Make It Go Faster – today more on PCIe, this time, Powering PCIe Cards with FPGAs… And with packets we mean: Networking using TCP/UDP/IP over 10G/25G/50G/100G Ethernet; PCI Express (PCIe), CXL, OpenCAPI; data storage using SATA, SAS, USB, NVMe; video image processing using HDMI, DisplayPort, SDI, FPD-III. To move packets you need power, but how much can you draw from an interface? PCI Express Cards Consumption Limit PCIe has been around for a long time, since 2003, and many people know the maximum power draw of 75W per PCIe slot, but is it that simple? The short answer is no, but let’s have a look into the spec. It states that all cards can consume up to 3A on the 3.3 V power rail with the following restrictions applying: x1 cards: 0,5A on 12V, but overall consumption limit is 10W x4 – x16 cards: 2,1A on 12V, but overall consumption limit is 25W But

Picking The Right Granularity When Buffering PCIe/NVMe Data

December 15, 2021FPGA DevTips, Storage AccelerationAMD/Xilinx ZCU106, BRAM, DRAM, HBM2, High Bandwidth Memory (HBM2), Memory Combination, PCI Express

Picking The Right Granularity When Buffering PCIe/NVMe Data Table of ContentsPicking The Right Granularity When Buffering PCIe/NVMe DataBlockRAM (BRAM)UltraRAM (URAM)DDRx DRAMHigh Bandwidth Memory (HBM2)Conclusion Non-Volatile Memory Express (NVMe) is an interface specification often used with PCIe. Its goal is to leverage the parallelism and low latency of modern SSDs. A typical PCIe payload data transfer happens in data chunks of either 128 Byte or 256 Byte. SSDs deploy several tricks (wear leveling, SLC to TLC conversion) to enhance the read and write speeds as well as their lifespan. One downside is that their read and write speed is not constant over a long write/read period which might result in backpressure. Some applications do not support back pressure that can lead to an erroneous state if one employs a standard SSD system. One possible mitigation strategy is to have an elastic buffer between the SSD and the data source. Using an FPGA, there are different possibilities to implement an elastic buffer. At MLE, we investigated BlockRAM (BRAM), UltraRAM (URAM), Dynamic RAM (DRAM) and the second generation of High Bandwidth Memory (HBM2). Each memory technology has its advantages and disadvantages regarding its capabilities to handle different data chunk sizes. We will present our findings below. BlockRAM (BRAM) BRAM is a RAM module which can