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Picking The Right Granularity When Buffering PCIe/NVMe Data You know our Mission: If It Is Packets, We Make It Go Faster – today the many flavors of memory for buffering data in FPGAs. Non-Volatile Memory Express (NVMe) is an interface specification often used with PCIe. Its goal is to leverage the parallelism and low latency of modern SSDs. A typical PCIe payload data transfer happens in data chunks of either 128 Byte or 256 Byte. SSDs deploy several tricks (wear leveling, SLC to TLC conversion) to enhance the read and write speeds as well as their lifespan. One downside is that their read and write speed is not constant over a long write/read period which might result in backpressure. Some applications do not support back pressure that can lead to an erroneous state if one employs a standard SSD system. One possible mitigation strategy is to have an elastic buffer between the SSD and the data source. Using an FPGA, there are different possibilities to implement an elastic buffer. At MLE, we investigated BlockRAM (BRAM), UltraRAM (URAM), Dynamic RAM (DRAM) and the second generation of High Bandwidth Memory (HBM2). Each memory technology has its advantages and disadvantages regarding its capabilities to handle different data chunk sizes. We will present our findings below.