High Level Synthesis for Intel and Xilinx FPGAs

Missing Link Electronics (MLE) has been an early adopter of High Level Synthesis (HLS) for FPGAs. In particular for Domain-Specific Architectures which aim to accelerate algorithms and communication protocols HLS delivers on the promised benefits:

  • Increased productivity as we can focus on the behavior and let HLS do the scheduling and resource mapping
  • Better portability across FPGA device families and even across FPGA device vendors

This MLE Technical Brief describes our findings when using HLS to accelerate a telecommunications network protocol accelerator with FPGA. Driven by the project’s need for short Time-to-Market major portions have been implemented in C/C++ using HLS. And given the application’s large unit volume it was important to evaluate cost/performance across a set of Intel and Xilinx FPGA devices.

Our example uses Intel and Xilinx HLS to implement a specialized Packet FIFO. This Packet FIFO is then integrated as a particular design block into a block-based top-level design. Despite the fact that Intel HLS and Xilinx HLS behave quite differently, and do require special code, we did see a benefit from using HLS compared to “classical” RTL design using VHDL and/or Verilog HDL.

Hence, we encourage the reader to follow a similar approach.

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