Shift-Left Your FPGA Design Projects

January 22, 2024Application Notes, Methodologies4K Image Processing, High-speed Data, Network Acceleration, NPAP, SmartNIC, Time-Sensitive Networking (TSN), Trenz

Shift-Left Your FPGA Design Projects

TB20231221

Summary

FPGA Full System Stacks comprising off-the-shelf FPGA System-on-Modules (SoM) plus pre-validated FPGA IP Cores and subsystems can greatly accelerate the time-to-market of your FPGA design project. Advantages of FPGA Full System Stacks include:

FPGA developers can rely on a tested and verified subsystem implementation. The concept of re-use increases design productivity while sharing the FPGA subsystem development costs and risks over many users.
Pre-validated FPGA IP-Cores and subsystems make clever use of the different FPGA resources to realize a cost/performance optimized domain-specific architecture.
Software is included in the form of kernel space device drivers, user-space programmer APIs, and sometimes even complete OS images, all nicely tuned for guaranteeing the overall system’s reliability and performance.

FPGA Full System Stacks from MLE are integrated with select FPGA SoMs from Trenz Electronics and are focused on applications such as:

Realiable, Low-Latency, High-Throughput Network Transports
High-Speed Data Acquisition
Augmented Stereo Computer Vision
High-Speed Data Record & Replay

We describe a design methodology using FPGA Full System Stacks and share our experiences from real customer designs.

High Level Synthesis for Intel and Xilinx FPGAs

July 7, 2021Application Notes, Methodologies

High Level Synthesis for Intel and Xilinx FPGAs

TB20201203

Version 1.0

Missing Link Electronics (MLE) has been an early adopter of High Level Synthesis (HLS) for FPGAs. In particular for Domain-Specific Architectures which aim to accelerate algorithms and communication protocols HLS delivers on the promised benefits:

Increased productivity as we can focus on the behavior and let HLS do the scheduling and resource mapping
Better portability across FPGA device families and even across FPGA device vendors

This MLE Technical Brief describes our findings when using HLS to accelerate a telecommunications network protocol accelerator with FPGA. Driven by the project’s need for short Time-to-Market major portions have been implemented in C/C++ using HLS. And given the application’s large unit volume it was important to evaluate cost/performance across a set of Intel and Xilinx FPGA devices.

Our example uses Intel and Xilinx HLS to implement a specialized Packet FIFO. This Packet FIFO is then integrated as a particular design block into a block-based top-level design. Despite the fact that Intel HLS and Xilinx HLS behave quite differently, and do require special code, we did see a benefit from using HLS compared to “classical” RTL design using VHDL and/or Verilog HDL.

Hence, we encourage the reader to follow a similar approach.

PCIe Non-Transparent Bridging (NTB)

April 24, 2019Application Notes, MethodologiesPCI Express, PCIe Non-Transparent Bridging (NTB)

Tool Options When Debugging an FPGA-based PCIe NTB Used in an ECU for Autonomous Driving

TB20190424

We share our findings and experiences when debugging an FPGA-based PCIe Non-Transparent Bridge (PCIe NTB) used in an Electronic Control Unit (ECU) for Autonomous Vehicles. After explaining key inner workings of PCIe and PCIe Non-Transparent Bridge we discuss debugging using embedded logic analyzers (Xilinx ChipScope / ILA), RTL Simulators (XSim from the Xilinx Vivado toolsuite as well as Questa Prime from Mentor Graphics) plus Visualizer, also from Mentor Graphics. We hope that you find this useful when you are preparing to debug your next FPGA project.