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    NPAP Datasheet

    Datasheet

    TCP/UDP/IPv4 Network Protocol Accelerator Platform (NPAP) Datasheet

    For the stand-alone TCP/UDP/IPv4 Stack Full-Accelerator Subsystem allowing communication at full line rate and low latency

    NPAP Datasheet

    NPAP Summary

    MLE’s Network Protocol Accelerator Platform (NPAP) is a proven TCP/UDP/IPv4 network protocol Full-Accelerator to enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for 1G / 2.5G / 5G / 10G / 25G / 40G / 50G / 100G / 400G Ethernet links.

    1. Features

    With a focus on reliability and low, deterministic latency, HHI designed this for embeddable FPGA and ASIC systems with the following features:

    • Interface to 1 / 2.5 / 5 / 10 / 25 / 40 / 50 / 100 / 200 / 400 Gigabit Ethernet 
    • Full-duplex with 128 bit wide bidirectional datapath 
    • Full line rate of 70 Gbps, or more, per instance in FPGA
    • Full line rate of over 100 Gbps per instance in ASIC
    • Low one-way latency NPAP-to-NPAP (600 nanoseconds for 100 Bytes)
    • Network diagnostics functions (optional)
    • TCP session priority management (optional)
    • Transport Layer Security (TLS) (optional)
    • Time-Sensitive Networking (TSN) (optional)
    • Network Impairment Generators (optional)

    Designed for maximum flexibility, NPAP implements in programmable logic the relevant network communication protocols:

    • IPv4 The core of the most standards-based networking protocols
    • TCP Reliable connectivity for direct secured connectivity
    • UDP Widespread protocol to enable simple direct or multicast communication
    • RRRRP Reliable, Rapid Request-Response Protocol based on Stanford HOMA
    • ICMPv4 Diagnostic protocol to validate connections
    • IGMPv4 Enables joining of multicast groups (optional)

    Due to the modularity NPAP can easily be enhanced by application specific protocols.

    The 128 bit wide datapath in combination with a pipelined architecture allows to scale throughput to line-rates of 50 GbE, and beyond, when using modern FPGA fabric, and up to 100 Gbps for ASIC implementations. NPAP is available in versions which recently have been merged:

    • Version 2 (currently 2.9.0) for new ASIC and AMD/Xilinx Versal, Ultrascale+, Ultrascale, Altera/Intel Agilex-7, Agilex-5E and Stratix-10, Microchip PolarFire and Lattice Avant G/X development, includes many recent resource optimizations plus timing optimizations focused on pipelines in FPGA, including Altera/Intel HyperFlex and Intel HyperFlex2
    • Version 1 (currently 1.10.1) back-ports bug fixes from Version 2 for long-term customer support. Not recommended for new design starts!

    Myth-Busting Latency Numbers for TCP Offload Engines

    Application Notes, Networking, , , ,

    Myth-Busting Latency Numbers for TCP Offload Engines

    TB20260224

    When you shop around for a TCP IP-Core for TCP offload engines, don’t you ask yourself: What does that really mean when you see numbers like this?

    This Technical Brief sheds light on TCP/IP processing in an FPGA, and in particular busts
    some myths about latency numbers. Here, we will describe proper ways of measuring
    latency numbers, and why latency numbers do matter when implementing TCP/IP in
    FPGAs.

    Based on MLE’s past projects experience, it all comes down to technical and economical
    feasibility determined by FPGA resource costs!

    Table of Contents

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    A TCP/IP Stack for High-Performance Chip-to-Chip

    Application Notes, Networking, , , , , ,

    A TCP/IP Stack for High-Performance Chip-to-Chip

    TB20250403

    Stream processing enables parallel data handling by creating pipelines of Stream Processing Elements (SPE) between a data source (typically a sensor) and a data sink (typically a decision maker), synchronized through back pressure. For multiple FPGA systems, the so-called AURORA protocol is frequently used in industrial, medical and scientific applications. However, TCP/IP over multi-Gigabit Ethernet can offer a more reliable and resource-efficient solution for distributed systems, in particular when FPGA devices are farther apart.

    This Technical Brief shares our experiment data, comparing the reliability and resource efficiency of Aurora protocol and TCP/IP, an MLE NPAP Full Accelerator running TCP/IP inside the programmable logic.

    Table of Contents

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    Analyzing Network Impairment and Signal Integrity in High-Speed TCP/UDP/IP Ethernet Networks

    Application Notes, Networking, , , , , , , , ,

    Analyzing Network Impairment and Signal Integrity
    in High-Speed TCP/UDP/IP Ethernet Networks

    TB20250327

    Summary

    MLE has been supporting customers in implementing distributed systems. MLE NPAP, the TCP/UDP/IP Stack originating from Fraunhofer HHI, has been one of the underlying technologies to connect FPGAs with each other as well as with servers and sensors reliably. 

    Customer implementations range from systems using a purpose-built LAN, or systems exposed to high levels of electro-magnetic inference (EMI), or rotating nodes using slip rings, or wireless. 

    Engineering teams often focus on delivering high throughput (close to linerate) and very low latency (i.e. a small Bandwidth-Delay-Product). Network impairment can quickly derail those engineering efforts. Therefore, MLE NPAP has built-in means to diagnose the effects of real-life network impairment. 

    This Technical Brief expands on analyzing network impairments and explains how these can be emulated when using Field-Programmable Gate Arrays (FPGAs), leading to technical insights allowing you to deliver better systems, faster.

    Table of Contents

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    Testdrive the Future of Networking: Evaluate MLE’s FPGA-Powered TCP/IP Stack in the Cloud!

    FPGA DevTips, Network Acceleration, , ,
    Testdrive The Future of Networking: Evaluate MLE’s FPGA-Powered TCP/IP Stack in the Cloud! Our Mission: If It Is Packets, We Make It Go Faster! And with packets we mean: Networking using TCP/UDP/IP over 10G/25G/50G/100G Ethernet PCI Express (PCIe), CXL, OpenCAPI Data storage using SATA, SAS, USB, NVMe Video image processing using HDMI, DisplayPort, SDI, FPD-III. In today’s fast-paced digital landscape, robust and efficient network communication is critical. For developers seeking to optimize network performance, MLE offers a groundbreaking solution: an FPGA-accelerated TCP/IP stack. Now, you can experience the power of this technology firsthand by evaluating it in our cloud-based environment, before committing to a hardware purchase. The Need for Speed: Overcoming Software Limitations Traditional software-based TCP/IP stacks often struggle to keep up with the demands of high-bandwidth, low-latency applications. Processing overhead can lead to bottlenecks and reduced efficiency. MLE’s FPGA-accelerated TCP/IP stack addresses these challenges by offloading network processing to dedicated hardware. The MLE Advantage: Hardware Acceleration for Optimal Performance Our Network Protocol Accelerator (NPAP) leverages the parallel processing capabilities of Field-Programmable Gate Arrays (FPGAs) to implement a full TCP/IP/UDP stack directly in hardware. This approach drastically reduces latency and maximizes throughput, offering a significant performance advantage over software-based solutions. Try Before You Buy: Cloud-Based Evaluation MLE understands the importance of thorough

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    Shift-Left Your FPGA Design Projects

    Application Notes, Methodologies, , , , , ,

    Shift-Left Your FPGA Design Projects

    TB20231221

    Summary

    FPGA Full System Stacks comprising off-the-shelf FPGA System-on-Modules (SoM) plus pre-validated FPGA IP Cores and subsystems can greatly accelerate the time-to-market of your FPGA design project. Advantages of FPGA Full System Stacks include:

    1. FPGA developers can rely on a tested and verified subsystem implementation. The concept of re-use increases design productivity while sharing the FPGA subsystem development costs and risks over many users.
    2. Pre-validated FPGA IP-Cores and subsystems make clever use of the different FPGA resources to realize a cost/performance optimized domain-specific architecture.
    3. Software is included in the form of kernel space device drivers, user-space programmer APIs, and sometimes even complete OS images, all nicely tuned for guaranteeing the overall system’s reliability and performance.

    FPGA Full System Stacks from MLE are integrated with select FPGA SoMs from Trenz Electronics and are focused on applications such as:

    • Reliable, Low-Latency, High-Throughput Network Transports
    • High-Speed Data Acquisition
    • Augmented Stereo Computer Vision
    • High-Speed Data Record & Replay

    We describe a design methodology using FPGA Full System Stacks and share our experiences from real customer designs.

    Table of Contents

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    High-Speed Data Acquisition Systems

    Application Notes, Networking, , , , , , , ,

    High-Speed Data Acquisition Systems

    TB20230713

    Challenges and design choices to network FPGAs and servers for high-speed data acquisition or retrieval. We discuss TCP/IP as a very fast transport when using TCP/IP full accelerators, in the sensor-side FPGA and in the server. 

    Table of Contents

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    Put a TCP/UDP/IP Turbo Into Your FPGA-SmartNIC

    Application Notes, Networking, , , , , ,

    Put a TCP/UDP/IP Turbo Into Your FPGA-SmartNIC

    TB20230523

    How MLE and Fraunhofer HHI are breaking the 500 MHz fMax barrier in network protocol acceleration (TCP/IP stack) by using Intel Agilex FPGAs as an FPGA SmartNIC.

    Summary

    MLE provides full system stacks including FPGAs, with a focus on networking for HPC, datacenter, or telecommunications. Often, we implement so-called full accelerators where almost all protocol processing runs efficiently within the FPGA fabric. 

    Within this Technical Brief we elaborate on two key aspects for FPGA-based SmartNICs: 

    1. How to implement rapid, reliable connectivity from edge to cloud using FPGA-based SmartNICs with TCP/IP stack acceleration, and 
    2. how these implementations can benefit from modern FPGA technology, namely Intel HyperFlex, to deliver better performance, cost and power.

    Our design choices for FPGA SmartNICs include the Corundum project, an open-source, high-performance FPGA-based Network Interface Card (NIC) platform. Corundum supports In-Network Processing for which we have integrated MLE’s Network Protocol Accelerator Platform (NPAP) based on the TCP/UDP/IP Full Accelerator from Fraunhofer HHI. 

    To enable network protocol processing at linerates of 100 Gbps, or faster, we have optimized this implementation for Intel HyperFlex architecture. The result is a “turbo charged” FPGA SmartNIC which combines several advantages:

    • NPAP with high throughput for those “heavy” TCP data streams which make up for most of the network traffic.
    • NPAP for those latency sensitive TCP connections where TCP round-trip time (RTT) may dominate the entire system’s response time.
    • Corundum processing in open-source Linux software for the rest, i.e. all those administrative and control TCP connections which hardly use any bandwidth and which are not latency sensitive.
    • Performance optimizations utilizing Intel HyperFlex to break the 500 MHz fMax barrier and to avoid FPGA resource “bloat”1.
    Table of Contents

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    Increase Speed and Save Resources with Simple Coding Style Changes

    FPGA DevTips, Network Acceleration, ,
    FPGA Programming – Increase Speed and Save Resources with Simple Coding Style Changes Table of ContentsFPGA Programming – Increase Speed and Save Resources with Simple Coding Style ChangesASIC vs. FPGA in Process AccelerationMLE Smart Process Redesign in FPGA Programming for Resource Saving and Speed Increasing ASIC vs. FPGA in Process Acceleration Compared to ASICs, FPGAs are a much more versatile option when it comes to accelerating processes with hardware, as an FPGA can be reconfigured and programmed as often as needed. However, one large benefit to ASICs is the possible maximum clock speed that can be reached. As its circuit is optimized for its specific function, it has a smaller footprint, resulting in a faster maximum clock speed. So one aspect of accelerating a process with FPGAs is not only just to redesign that process in hardware and hoping for faster results, but to smartly redesign that process to use as little hardware space as possible, resulting in a higher maximum clock speed. As engineers we know, there is always room for improvement, so we at Missing Link Electronics strive to continuously improve our existing product lineup. MLE Smart Process Redesign in FPGA Programming for Resource Saving and Speed Increasing In one of these development cycles, we encountered a simple, yet very

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    Latency Measurement of 10G/25G/50G/100G TCP-Cores using RTL Simulation

    Application Notes, Networking, , ,

    Latency Measurement of 10G/25G/50G/100G TCP-Cores using RTL Simulation

    TB20220305

    Distributed Systems-of-Systems which, for example, connect smart sensor hubs with centralized processing via Ethernet, require very low transport latencies in order to deliver short response times. This makes it difficult for system designers to evaluate. And, things get worse if the measurement setup and methodology is not clearly explained, neither can be reproduced. Therefore, in this Technical Brief we describe how we use the Questa Advanced Simulator from Siemens EDA to measure network latency and analyze latency in a network protocol processing system. And, we also provide the most recent latency values for NPAP, the TCP/IP Stack from Fraunhofer HHI which is, as it turns out, very competitive with other solutions. Being integrators ourselves, we believe we owe this to the FPGA ecosystem!

    Table of Contents

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