Shift-Left Your FPGA Design Projects

Application Notes, Methodologies, , , , , ,

Shift-Left Your FPGA Design Projects

TB20231221

Summary

FPGA Full System Stacks comprising off-the-shelf FPGA System-on-Modules (SoM) plus pre-validated FPGA IP Cores and subsystems can greatly accelerate the time-to-market of your FPGA design project. Advantages of FPGA Full System Stacks include:

  1. FPGA developers can rely on a tested and verified subsystem implementation. The concept of re-use increases design productivity while sharing the FPGA subsystem development costs and risks over many users.
  2. Pre-validated FPGA IP-Cores and subsystems make clever use of the different FPGA resources to realize a cost/performance optimized domain-specific architecture.
  3. Software is included in the form of kernel space device drivers, user-space programmer APIs, and sometimes even complete OS images, all nicely tuned for guaranteeing the overall system’s reliability and performance.

FPGA Full System Stacks from MLE are integrated with select FPGA SoMs from Trenz Electronics and are focused on applications such as:

  • Realiable, Low-Latency, High-Throughput Network Transports
  • High-Speed Data Acquisition
  • Augmented Stereo Computer Vision
  • High-Speed Data Record & Replay

We describe a design methodology using FPGA Full System Stacks and share our experiences from real customer designs.

Read More

High-Speed Data Acquisition Systems

Application Notes, Networking, , , , , , , ,

High-Speed Data Acquisition Systems

TB20230713

Challenges and design choices to network FPGAs and servers for high-speed data acquisition or retrieval. We discuss TCP/IP as a very fast transport when using TCP/IP full accelerators, in the sensor-side FPGA and in the server. 

Read More

Put a TCP/UDP/IP Turbo Into Your FPGA-SmartNIC

Application Notes, Networking, , , , , ,

Put a TCP/UDP/IP Turbo Into Your FPGA-SmartNIC

TB20230523

How MLE and Fraunhofer HHI are breaking the 500 MHz fMax barrier in network protocol acceleration (TCP/IP stack) by using Intel Agilex FPGAs as an FPGA SmartNIC.

Summary

MLE provides full system stacks including FPGAs, with a focus on networking for HPC, datacenter, or telecommunications. Often, we implement so-called full accelerators where almost all protocol processing runs efficiently within the FPGA fabric. 

Within this Technical Brief we elaborate on two key aspects for FPGA-based SmartNICs: 

  1. How to implement rapid, reliable connectivity from edge to cloud using FPGA-based SmartNICs with TCP/IP stack acceleration, and 
  2. how these implementations can benefit from modern FPGA technology, namely Intel HyperFlex, to deliver better performance, cost and power.

Our design choices for FPGA SmartNICs include the Corundum project, an open-source, high-performance FPGA-based Network Interface Card (NIC) platform. Corundum supports In-Network Processing for which we have integrated MLE’s Network Protocol Accelerator Platform (NPAP) based on the TCP/UDP/IP Full Accelerator from Fraunhofer HHI. 

To enable network protocol processing at linerates of 100 Gbps, or faster, we have optimized this implementation for Intel HyperFlex architecture. The result is a “turbo charged” FPGA SmartNIC which combines several advantages:

  • NPAP with high throughput for those “heavy” TCP data streams which make up for most of the network traffic.
  • NPAP for those latency sensitive TCP connections where TCP round-trip time (RTT) may dominate the entire system’s response time.
  • Corundum processing in open-source Linux software for the rest, i.e. all those administrative and control TCP connections which hardly use any bandwidth and which are not latency sensitive.
  • Performance optimizations utilizing Intel HyperFlex to break the 500 MHz fMax barrier and to avoid FPGA resource “bloat”1.

Read More

Increase Speed and Save Resources with Simple Coding Style Changes

FPGA DevTips, Network Acceleration, ,
Increase Speed and Save Resources with Simple Coding Style Changes Our Mission: If It Is Packets, We Make It Go Faster! And with packets we mean: Networking using TCP/UDP/IP over 10G/25G/50G/100G Ethernet; PCI Express (PCIe), CXL, OpenCAPI; data storage using SATA, SAS, USB, NVMe; video image processing using HDMI, DisplayPort, SDI, FPD-III. Over the last decade, we have become experts in accelerating software-rich system stacks via offloading CPUs using so-called Domain-Specific Architectures for computing. For implementation, we make heavy use of heterogeneous processing devices such as FPGAs which we program using C++/C/SystemC as well as VHDL and Verilog HDL. ASIC vs. FPGA in Process Acceleration Compared to ASICs, FPGAs are a much more versatile option when it comes to accelerating processes with hardware, as an FPGA can be reconfigured as often as needed. However, one large benefit to ASICs is the possible maximum clock speed that can be reached. As its circuit is optimized for its specific function, it has a smaller footprint, resulting in a faster maximum clock speed. So one aspect of accelerating a process with FPGAs is not only just to redesign that process in hardware and hoping for faster results, but to smartly redesign that process to use as little hardware space as possible, resulting in a higher

Read More

Latency Measurement of 10G/25G/50G/100G TCP-Cores using RTL Simulation

Application Notes, Networking, , ,

Latency Measurement of 10G/25G/50G/100G TCP-Cores using RTL Simulation

TB20220305

Distributed Systems-of-Systems which, for example, connect smart sensor hubs with centralized processing via Ethernet, require very low transport latencies in order to deliver short response times. This makes it difficult for system designers to evaluate. And, things get worse if the measurement setup and methodology is not clearly explained, neither can be reproduced. Therefore, in this Technical Brief we describe how we use the Questa Advanced Simulator from Siemens EDA to measure network latency and analyze latency in a network protocol processing system. And, we also provide the most recent latency values for NPAP, the TCP/IP Stack from Fraunhofer HHI which is, as it turns out, very competitive with other solutions. Being integrators ourselves, we believe we owe this to the FPGA ecosystem!

Read More

NPAP-10G Remote Evaluation

Remote Evals,

NPAP-10G Remote Evaluation

Try out MLE’s Network Protocol Accelerator Platform based on the TCP/UDP/IP Full Accelerator from German Fraunhofer Heinrich-Hertz-Institute!

The MLE-NPAP Remote Evaluation will give you first hands on experience of the performance and usability of a TCP/UDP full accelerator. The advantage of MLE NPAP is the standalone capability of the stack, which means no CPU is required to send and receive data. This allows data rates near line rate.

Read More

CONTACT MLE

Please fill in the form below, so we can give you access to the Remote Evaluation System.


    NPAP-10G Remote Eval.NPAP-25G Remote Eval.


    X
    CONTACT MLE