Put a TCP/UDP/IP Turbo Into Your FPGA-SmartNIC
How MLE and Fraunhofer HHI are breaking the 500 MHz fMax barrier in network protocol acceleration by using Intel Agilex FPGAs as an FPGA SmartNIC.
MLE provides full system stacks including FPGAs, with a focus on networking for HPC, datacenter, or telecommunications. Often, we implement so-called full accelerators where almost all protocol processing runs efficiently within the FPGA fabric.
Within this Technical Brief we elaborate on two key aspects for FPGA-based SmartNICs:
- How to implement rapid, reliable connectivity from edge to cloud using FPGA-based SmartNICs with TCP/IP acceleration, and
- how these implementations can benefit from modern FPGA technology, namely Intel HyperFlex, to deliver better performance, cost and power.
Our design choices for FPGA SmartNICs include the Corundum project, an open-source, high-performance FPGA-based Network Interface Card (NIC) platform. Corundum supports In-Network Processing for which we have integrated MLE’s Network Protocol Accelerator Platform (NPAP) based on the TCP/UDP/IP Full Accelerator from Fraunhofer HHI.
To enable network protocol processing at linerates of 100 Gbps, or faster, we have optimized this implementation for Intel HyperFlex architecture. The result is a “turbo charged” FPGA SmartNIC which combines several advantages:
- NPAP with high throughput for those “heavy” TCP data streams which make up for most of the network traffic.
- NPAP for those latency sensitive TCP connections where TCP round-trip time (RTT) may dominate the entire system’s response time.
- Corundum processing in open-source Linux software for the rest, i.e. all those administrative and control TCP connections which hardly use any bandwidth and which are not latency sensitive.
- Performance optimizations utilizing Intel HyperFlex to break the 500 MHz fMax barrier and to avoid FPGA resource “bloat”1.