Shift-Left Your FPGA Design Projects

January 22, 2024Application Notes, Methodologies4K Image Processing, High-speed Data, Network Acceleration, NPAP, SmartNIC, Time-Sensitive Networking (TSN), Trenz

Shift-Left Your FPGA Design Projects

TB20231221

Summary

FPGA Full System Stacks comprising off-the-shelf FPGA System-on-Modules (SoM) plus pre-validated FPGA IP Cores and subsystems can greatly accelerate the time-to-market of your FPGA design project. Advantages of FPGA Full System Stacks include:

FPGA developers can rely on a tested and verified subsystem implementation. The concept of re-use increases design productivity while sharing the FPGA subsystem development costs and risks over many users.
Pre-validated FPGA IP-Cores and subsystems make clever use of the different FPGA resources to realize a cost/performance optimized domain-specific architecture.
Software is included in the form of kernel space device drivers, user-space programmer APIs, and sometimes even complete OS images, all nicely tuned for guaranteeing the overall system’s reliability and performance.

FPGA Full System Stacks from MLE are integrated with select FPGA SoMs from Trenz Electronics and are focused on applications such as:

Realiable, Low-Latency, High-Throughput Network Transports
High-Speed Data Acquisition
Augmented Stereo Computer Vision
High-Speed Data Record & Replay

We describe a design methodology using FPGA Full System Stacks and share our experiences from real customer designs.

Put a TCP/UDP/IP Turbo Into Your FPGA-SmartNIC

May 23, 2023Application Notes, Networking10/25/50/100G Ethernet, Intel, Network Acceleration, Network Protocol Accelerator, NPAP, SmartNIC, TCP/IP

Put a TCP/UDP/IP Turbo Into Your FPGA-SmartNIC

TB20230523

How MLE and Fraunhofer HHI are breaking the 500 MHz fMax barrier in network protocol acceleration (TCP/IP stack) by using Intel Agilex FPGAs as an FPGA SmartNIC.

Summary

MLE provides full system stacks including FPGAs, with a focus on networking for HPC, datacenter, or telecommunications. Often, we implement so-called full accelerators where almost all protocol processing runs efficiently within the FPGA fabric.

Within this Technical Brief we elaborate on two key aspects for FPGA-based SmartNICs:

How to implement rapid, reliable connectivity from edge to cloud using FPGA-based SmartNICs with TCP/IP stack acceleration, and
how these implementations can benefit from modern FPGA technology, namely Intel HyperFlex, to deliver better performance, cost and power.

Our design choices for FPGA SmartNICs include the Corundum project, an open-source, high-performance FPGA-based Network Interface Card (NIC) platform. Corundum supports In-Network Processing for which we have integrated MLE’s Network Protocol Accelerator Platform (NPAP) based on the TCP/UDP/IP Full Accelerator from Fraunhofer HHI.

To enable network protocol processing at linerates of 100 Gbps, or faster, we have optimized this implementation for Intel HyperFlex architecture. The result is a “turbo charged” FPGA SmartNIC which combines several advantages:

NPAP with high throughput for those “heavy” TCP data streams which make up for most of the network traffic.
NPAP for those latency sensitive TCP connections where TCP round-trip time (RTT) may dominate the entire system’s response time.
Corundum processing in open-source Linux software for the rest, i.e. all those administrative and control TCP connections which hardly use any bandwidth and which are not latency sensitive.
Performance optimizations utilizing Intel HyperFlex to break the 500 MHz fMax barrier and to avoid FPGA resource “bloat”¹.