TCP/UDP/IPv4 Network Protocol Accelerator Platform (NPAP) Datasheet
For the stand-alone TCP/UDP/IPv4 Stack Full-Accelerator Subsystem allowing communication at full line rate and low latency
NPAP Datasheet
- 1. NPAP Features
- 2. NPAP Applications
- 3. NPAP Functionality Description
- 3.1. NPAP Technical Features
- 3.2. NPAP Implementation Details
- 3.3. NPAP Dataflow and Block Diagram
- 3.4. NPAP Control-Flow View and Hardware Abstraction Layer
- 3.5. NPAP Evaluation Choices
- 3.6. IP Core Deliverables
- 3.7. Optional Diagnostics and Network Statistics
- 3.8. Optional Benchmarking using Netperf
- 3.9. Network Impairment and Bit Error Insertion
- 4. System-Level Architecture Using TCP/UDP/IPv4
- 4.1. Picking the “Right” TCP Peer
- 4.2. Picking the Right TCP Rx/Tx Buffer Sizes
- 4.3. Picking the Right Number of TCP Cores
- 4.4. Optimizing NPAP for Linerate Performance
- 4.5. Hybrid Acceleration by Combining NPAP With FPGA Network Interface Cards (NIC)
- 4.6. Implementing Time-Sensitive Networking (TSN)
- 4.7. Linux Kernel Bypass With NPAP
- 4.8. Latency Analysis Results
- 4.9. Optional Transport Layer Security (TLS)
- 5.1. FPGA Resource Estimates
- 6. Network Administration for NPAP
- 7. System Verification via RTL Simulation
- 8. Developer Documentation
- 9. Changelog
- 10. Detailed Protocol Support (RFC1122 excerpt)
NPAP Summary
MLE’s Network Protocol Accelerator Platform (NPAP) is a proven TCP/UDP/IPv4 network protocol Full-Accelerator to enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for 1G / 2.5G / 5G / 10G / 25G / 40G / 50G / 100G / 400G Ethernet links.
1. Features
With a focus on reliability and low, deterministic latency, HHI designed this for embeddable FPGA and ASIC systems with the following features:
- Interface to 1 / 2.5 / 5 / 10 / 25 / 40 / 50 / 100 / 200 / 400 Gigabit Ethernet
- Full-duplex with 128 bit wide bidirectional datapath
- Full line rate of 70 Gbps, or more, per instance in FPGA
- Full line rate of over 100 Gbps per instance in ASIC
- Low one-way latency NPAP-to-NPAP (600 nanoseconds for 100 Bytes)
- Network diagnostics functions (optional)
- TCP session priority management (optional)
- Transport Layer Security (TLS) (optional)
- Time-Sensitive Networking (TSN) (optional)
- Network Impairment Generators (optional)
Designed for maximum flexibility, NPAP implements in programmable logic the relevant network communication protocols:
- IPv4 The core of the most standards-based networking protocols
- TCP Reliable connectivity for direct secured connectivity
- UDP Widespread protocol to enable simple direct or multicast communication
- RRRRP Reliable, Rapid Request-Response Protocol based on Stanford HOMA
- ICMPv4 Diagnostic protocol to validate connections
- IGMPv4 Enables joining of multicast groups (optional)
Due to the modularity NPAP can easily be enhanced by application specific protocols.
The 128 bit wide datapath in combination with a pipelined architecture allows to scale throughput to line-rates of 50 GbE, and beyond, when using modern FPGA fabric, and up to 100 Gbps for ASIC implementations. NPAP is available in versions which recently have been merged:
- Version 2 (currently 2.9.0) for new ASIC and AMD/Xilinx Versal, Ultrascale+, Ultrascale, Altera/Intel Agilex-7, Agilex-5E and Stratix-10, Microchip PolarFire and Lattice Avant G/X development, includes many recent resource optimizations plus timing optimizations focused on pipelines in FPGA, including Altera/Intel HyperFlex and Intel HyperFlex2
- Version 1 (currently 1.10.1) back-ports bug fixes from Version 2 for long-term customer support. Not recommended for new design starts!