5.1. Resource Estimates for AMD Versal AI Edge Series
- 5.1. Resource Estimates for AMD Versal AI Edge Series
- 5.2. Resource Estimates for AMD/Xilinx Ultrascale+ Series
- 5.3. Resource Estimates for AMD/Xilinx 7-Series
- 5.4. Resource Estimates for Altera/Intel Agilex 5E
- 5.5. Resource Estimates for Altera/Intel Stratix-10
- 5.6. Resource Estimates for Lattice Avant-G
- 5.7. Resource Estimates for Microchip Polarfire
The following table shows resources for AMD/Xilinx Versal AI Edge Series fabric (xcve2302-sfva784-1LP-e-S-es1) compiled with AMD/Xilinx Vivado/Vitis 2024.1 – instantiating the following design features:
- Ethernet block
- IPv4 block
- 1 UDP block
- 4 instances of TCP blocks
- Diagnostics blocks
5.2. Resource Estimates for AMD/Xilinx Ultrascale+ Series
The following table shows resources for AMD/Xilinx Zynq Ultrascale+ MPSoC ZU9EG compiled with AMD/Xilinx Vivado 2022.2 – instantiating the following design features:
- 10 GigE Low-Latency MAC from Fraunhofer HHI
- Ethernet block
- IPv4 block
- UDP block
- 10 instances of TCP blocks (2 used for netperf)
- TCP and UDP Diagnostics blocks
- 10 GigE Low-Latency MAC from Fraunhofer HHI
- Ethernet block
- IPv4 block
- UDP block
- 10 instances of TCP
5.3. Resource Estimates for AMD/Xilinx 7-Series
The following table shows resources for AMD/Xilinx 7-Series Kintex fabric (XC7Z045-2) compiled with AMD/Xilinx Vivado 2014.4 – instantiating the following design features:
- 10 GigE Low-Latency MAC from Fraunhofer HHI
- Ethernet block
- IPv4 block
- UDP block
- 2 instances of TCP blocks
- No diagnostics
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