4.8. Latency Analysis Results

4.8. Latency Analysis Results MLE analyzed processing latency using RTL simulation of two instances of NPAP (using different clock speeds) connected via 10G LL MAC via XGMII (clocked at 156.25 MHz). TCP Payload Size [Byte]Clock cyclesLatency [ns] at 175 MHzLatency [ns] at 322 MHzLatency [ns] at 550 MHz162354.3192.5112.73267382.9208.1121.86473417.1226.7132.716091520.0282.6165.5448145828.6450.3263.69602411,377.1748.4438.212162891,651.4897.5525.514563341,908.61,037.3607.3 Latency was measured “one-way, door-to-door”: Using RTL simulation we count the number of clock cycles it takes from sending payload data from one NPAP instance (TX) via the full NPAP kernel until the other instance of NPAP receives that payload data (RX). Here the system-level block diagram: Obviously, increasing the NPAP clock frequency will reduce latency for asynchronous NPAP subsystems. More information on dependable latency numbers can be found in our Technical Brief “Myth-Busting Latency Numbers for TCP Offload Engines.” Myth-Busting Latency Numbers for TCP Offload Engines 🌐 www.missinglinkelectronics.com MLE (Missing Link Electronics) is offering technologies and solutions for Domain-Specific Architectures, which focus on heterogeneous computing using FPGAs. MLE is headquartered in Silicon Valley with offices in Neu-Ulm and Berlin, Germany.