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    A TCP/IP Stack for High-Performance Chip-to-Chip

    Stream processing enables parallel data handling by creating pipelines of Stream Processing Elements (SPE) between a data source (typically a sensor) and a data sink (typically a decision maker), synchronized through back pressure. When multiple FPGAs are used, AURORA protocol is ideal for single-board setups, while TCP/IP over multi-Gigabit Ethernet offers a more reliable and resource-efficient solution for distributed systems where FPGA devices are farther apart. TCP/IP also ensures low-latency data transport, higher throughput, and increased clock frequencies.

    This Technical Brief shares our experiment data, comparing the reliability and resource efficiency of Aurora protocol and TCP/IP, an MLE NPAP Full Accelerator running TCP/IP inside the programmable logic.


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